MOUNTAIN VIEW, Calif., Sept. 20, 2021 / PRNewswire / –
Highlights of this announcement:
- Synopsys ARC 128-bit VPX2 and 256-bit VPX3 DSP IP are based on the same advanced VLIW / SIMD architecture as the more powerful 512-bit VPX5 and offer more flexibility for specific application requirements
- The portfolio includes security-enhanced implementations that meet the requirements of random error detection and the systematic development process of functional safety for full conformity with ISO 26262 to ASIL D. fulfill
- MetaWare Development Toolkit with C / C ++ compiler and associated libraries supports vector-length independent programming to accelerate code development and portability
- Attend the ARC Processor Virtual Summit from September 21-22, 2021 to learn more about the new ARC VPX DSPs and the latest technologies and trends in processor IP
To meet the broader power, power, and area (PPA) requirements of embedded applications, Synopsys, Inc. (Nasdaq: SNPS) announced today that it has expanded its DesignWareÂ® ARCÂ® processor IP portfolio to include new 128- Bit ARC VPX2 and 256. has expanded the -bit ARC VPX3 DSP processors. Based on the same VLIW / SIMD architecture as the company’s more powerful 512-bit ARC VPX5 DSP processor, the new additions offer up to two thirds less performance and space. The ARC VPX DSP IP family now gives designers more flexibility to tailor their designs based on the unique power, power and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and LiDAR processing, motor control, voice / speech recognition to optimize natural language processing and other edge AI applications.
“AI-enabled devices have an increasing need for specialized processors that can handle a wide variety of DSP and machine learning workloads with a high level of energy efficiency,” said CL Chen, COO at Neuchips, a leading AI domain-specific startup Computing solutions in Taiwan. “By expanding the ARC VPX processor family to support a range of vector lengths, Synopsys enables developers targeting a wider range of applications to implement powerful signal processing in their designs.”
“By adding support for smaller vectors to the ARC-DSP processor portfolio, Synopsys enables signal processing and AI in size, performance and thermal constrained systems,” said Jim McGregor, Principal Analyst at Tirias Research. âIn addition, thanks to their ultra-high floating point performance and compliance with functional safety, the VPX processors are particularly suitable for the growing number of IoT applications such as automobiles, medical technology and industrial automation. Synopsys ARC processors have been used by over 250 customers worldwide who collectively ship more than 2.5 billion ARC-based chips annually. “
Scalable and highly configurable DSP processors
The shorter vector length ARC VPX2 and VPX3 DSP processors, optimized for highly parallel processing with minimal power and space consumption, are available in single or dual core configurations to meet a wide range of application requirements. Each VPX core contains a scalar execution unit and multiple vector units that support 8-bit, 16-bit, and 32-bit SIMD computations. The VPX DSPs support half, single, and double precision floating point formats, and up to three floating point pipelines are available in each VPX core. The unique hardware acceleration for special math functions used in linear and nonlinear algebra functions provides highly accurate results. The new VPX DSPs include improvements to the Instruction Set Architecture (ISA) and load / store bandwidth to deliver up to twice the performance of existing offerings for common DSP functions such as Fast Fourier Transforms (FFTs). In addition, the security-enhanced ARC VPX2FS and VPX3FS incorporate hardware security features, including error correction code (ECC) protection for memory and interfaces, safety monitors, and lockstep mechanisms that help developers achieve the strictest levels of ISO 26262 ASIL B, ASIL C, and compliance functional safety ASIL D.
Comprehensive software development environment
Like all Synopsys ARC processors, the VPX2 and VPX3 processors are supported by the Synopsys ARC MetaWare Development Toolkit, which provides a vector length independent software programming model optimized specifically for the VPX hardware architecture. The MetaWare compiler’s auto-vectorization feature converts sequential code into vector operations for maximum throughput. Along with a robust set of software libraries that include DSP, machine learning, and linear algebra functions, the MetaWare Development Toolkit provides a comprehensive programming environment that speeds time to optimal results and simplifies software portability.
“We are building our industry leadership by adding the latest VPX DSP processors to the DesignWare ARC processor family,” said John Koeter, Synopsys senior vice president of Marketing and Strategy for IP. “Synopsys offers designers a full range of scalable, software-compatible DSP-IP solutions that meet the various power, performance and space requirements within a chip family.”
The broad Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded tests, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, the company’s IP Accelerated Initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys’ extensive investment in IP quality and extensive technical support enable designers to reduce integration risk and accelerate time to market. Please visit https://www.synopsys.com/designware for more information.
- The Synopsys DesignWare ARC VPX2 and VPX3 DSP processor IP is expected to be available to leading customers in the fourth quarter of 2021.
- The Synopsys DesignWare ARC VPX2FS and VPX3FS processor IP is expected to be available to leading customers in the first quarter of 2022.
More information can be found here.
Virtual ARC Processor Summit, 21.-22. September 2021
The ARC Processor Virtual Summit gives you all the hands-on knowledge you need to meet your unique PPA needs. The summit includes a special keynote, TinyML and Efficient Deep Learning from Song Han, Assistant Professor for EECS at MIT. Han will teach TinyML techniques that will help you meet the extraordinary demands of artificial intelligence (AI) for data, computation and performance in a way that makes your designs greener, faster, more efficient and more sustainable. Register to attend the event.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software â¢ partner for innovative companies creating electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history as a global leader in electronic design automation (EDA) and semiconductor IP, offering the broadest portfolio of application security testing tools and services in the industry. Whether you are a system-on-chip (SoC) designer developing advanced semiconductors or a software developer writing more secure, high quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at www.synopsys.com.
Editorial contact: Simone Souza Synopsys, Inc. 650-584-6454 [email protected]
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SOURCE Synopsys, Inc.